Semiconductor packaging using copper pillar bump flip-chip interconnect technology has been widely adopted. Copper pillar bumps are used as the flip chip interconnect between the integrated circuit chip and the package substrate. Copper pillar bump flip-chip interconnect is a type of wafer level packaging where copper pillar bumps are formed on the bond pads of the integrated circuit die after the wafer processing is completed but before the wafer is diced into individual integrated circuit die. More specifically, at the end of wafer processing, the wafer is coated with a final dielectric layer, referred to as the passivation layer, which covers all of the active circuitry of the integrated circuit with only the bond pads exposed. The passivation layer is typically formed using silicon dioxide or silicon nitride. The back end processing of the wafer can then begin where the wafer is processed to form copper pillar bumps on the exposed bond pads of the wafer. After the copper pillar bumps are formed, the wafer is then diced into individual integrated circuit die and each integrated circuit die is assembled in flip-chip configuration onto a package substrate where the copper pillar bumps are used as the flip-chip interconnects to the package substrate.
FIG. 1 is a cross-sectional view of a packaged integrated circuit employing copper pillar bump flip-chip interconnect technology in some examples. Referring to FIG. 1, an integrated circuit die 12 is packaged in a flip-chip semiconductor package 10. The front side of the integrated circuit die 12, including the active circuitry and the bond pads for external connections, is faced downward in the package. Copper pillar bumps 14 are formed on the bond pads of the integrated circuit 12 and are used as the electrical interconnects between the integrated circuit die 12 and a package substrate 20, usually formed as a printed circuit board (PCB) substrate. The integrated circuit die 12 is flip-chip attached to the package substrate 20. An underfiller material 16 and a dam 18 may be used in the flip-chip attach process.
The PCB package substrate 20 may be a single layer or a multi-layer PCB. The PCB package substrate 20 includes conductive traces printed thereon and formed in the PCB for receiving the copper pillar bumps formed on the integrated circuit die 12 and for electrically connecting the copper pillar bumps formed on the top side of the substrate to an array of solder balls 22 formed on the bottom side of the substrate. The solder balls 22 form the external connections of the semiconductor package 10.
In the present illustration, the integrated circuit die is formed as a silicon on insulator integrated circuit. In the case that the integrated circuit die is used in high voltage applications, there can be significant charge build up on the insulator substrate on the backside of integrated circuit die 12. In some examples, the backside of the integrated circuit die 12 needs to be grounded. Accordingly, a conductive top substrate 26 is formed on the backside of integrated circuit die 12 and attached to the backside through a conductive adhesive 24. A bond wire 28 is used to electrically connect the top substrate 26 to the package substrate 20 for the electrical ground connection. The entire structure is then encapsulated in a mold compound 29 to form the semiconductor package 10.
In the copper pillar bump flip-chip interconnect process, packaging failures due to die warpage have been observed. FIG. 2 illustrates the package failure mode due to die warpage in one example. In the flip-chip interconnect process, after the copper pillar bumps are formed on the wafer, the wafer is subjected to backgrinding to a certain desired die thickness. For example, the wafer may have a thickness of 700 μm and is background to about 100 μm. Then, the wafer is diced up into individual die 12. After being diced up, certain stresses on the integrated circuit die 12 cause the die to warp, as shown in FIG. 2. The warpage on the die 12 prevents the die from being properly attached to the package substrate 20. In particular, due to the die warpage, some of the copper pillar bumps will not be able to make physical contact with the conductive traces on the package substrate 20, leading to open connections at the corners of the die, as shown in FIG. 2.
The die warpage issue typically affects integrated circuit die having a large die size, such as 10 mm×10 mm, and a thin die thickness, such as 100 μm. In some cases, the die warpage can be up to 70 μm, which is 70% of the die thickness. The die warpage issue on integrated circuit dies with large die size but thin die thickness makes flip-chip bonding onto a printed circuit board substrate impossible.
Conventional solutions to the die warpage issue involve increasing the die thickness, such as to backgrind the wafer only to 200 μm or 250 μm thickness. However, a thicker die size is sometimes not desirable as the package thickness is also increased, making the semiconductor package undesirable for certain applications, such as in small mobile devices. In some cases, it is believed that the die warpage is due to the polyimide material applied to the front surface of the integrated circuit die during the back end processing to form the copper pillar bumps. Thus, some conventional solution to the die warpage issue involves using polyimide material with lower curing temperature or lower flex modulus property on the integrated circuit die. These substitution materials sometimes increase the cost of the semiconductor package.